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W6811 single channel voicecodec revision a1 5 - 1 - january 201 1 1. general descripti on the W6811 is a general - purpose single channel pcm codec with pin - selectable u - law or a - law companding . the device is compliant with the itu g.712 specification . it operates off of separated analog (5v) and digital (3v) power suppli es and is available in 24 - pin sog, and ssop package options . functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for pcm systems . the filters are compliant with itu g.712 specific ation . W6811 performance is specified over the industrial temperature range of C 40 ? c to +85 ? c. the W6811 includes an on - chip precision voltage reference and an additional power amplifier, capable of driving 300 ? loads differentially up to a level of 6.3v peak - to - peak . the analog section is fully differential, reducing noise and improving the power supply rejection ratio . the data transfer protocol supports both long - frame and short - frame synchronous communications for pcm applications, and idl and gci c ommunications for isdn applications . W6811 accepts seven master clock rates between 256 khz and 4.096 mhz, and an on - chip pre - scaler automatically determines the division ratio for the required internal clock. 2. features ? power supply: ? analog 4.5 C 5.5v ? digital 2.7 C 3.3v ? typical power dissipation of 25 mw, power - down mode of 0.5 ?w ? fully - differential analog circuit design ? on - chip precision reference of 1.575 v for a 0 dbm tlp at 600 ? ? push - pull power amplifiers with external gain adjustment with 300 ? load capability ? seven master clock rates of 256 khz to 4.096 mhz ? pin - selectable ? - law and a - law companding (compliant with itu g.711) ? codec a/d and d/a filtering compliant with itu g.712 ? industrial temperature range ( C 40 ? c to +85 ? c) ? p ackage: 24 - pin sog, and ssop ? pb - free / rohs package options available applications ? digital telephone systems ? central office equipment (gateways, switches, routers) ? pbx systems (gateways, switches) ? pabx/soho systems ? local loop card ? soho routers ? voip terminals ? enterprise phones ? isdn terminals ? anal og line cards ? digital voice recorders www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 2 - january 201 1 3. block diagram 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz & 4096 khz mclk 256 khz 8 khz 512 khz pre - scaler v dda v ssa power conditioning voltage reference v ag pui g.712 codec g.711 ? /a - law pao+ pao - pai ro - ao ai+ ai - ? /a - law tra ns mit pc m int erf ace re cei ve pc m int erf a ce fst bclkt pcmt fsr bclkr pcmr v ref 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz & 4096 khz mclk 256 khz 8 khz pre - saler power conditioning voltage reference v ag g.712 codec g.711 ? /a - law ro ? /a - law g.712 codec g.711 ? /a - law ro ? /a - law transmit pcm interface receive pcm interface bclkt bclkt bclkr v v ddd v ssd www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 3 - january 201 1 4. table of contents 1. general descripti on ................................ ................................ ................................ ................................ ... 1 2. features ................................ ................................ ................................ ................................ .......................... 1 3. block diagram ................................ ................................ ................................ ................................ ............... 2 4. table of contents ................................ ................................ ................................ ................................ ....... 3 5 . pin configuration ................................ ................................ ................................ ................................ ........ 4 6. pin description ................................ ................................ ................................ ................................ .............. 5 7. functional descri ption ................................ ................................ ................................ ............................. 7 7.1. transmit path ................................ ................................ ................................ ................................ ............... 7 7.2. receive path ................................ ................................ ................................ ................................ ................ 8 7.3. power management ................................ ................................ ................................ ................................ ..... 9 7.3.1. analog supply ................................ ................................ ................................ ................................ ....... 9 7.3.2. digital supply ................................ ................................ ................................ ................................ ........ 9 7.3.3. analog ground reference bypass ................................ ................................ ................................ ....... 9 7.3.4. analog ground reference voltage output ................................ ................................ ........................... 9 7.4. pcm interface ................................ ................................ ................................ ................................ .............. 9 7.4.1. long frame sync ................................ ................................ ................................ ............................... 10 7.4.2. short frame sync ................................ ................................ ................................ ............................... 10 7.4.3. general circuit interface (gci) ................................ ................................ ................................ ........... 10 7.4.4. interchip digital link (idl) ................................ ................................ ................................ .................. 11 7.4.5. system timing ................................ ................................ ................................ ................................ .... 11 8. timing diagrams ................................ ................................ ................................ ................................ .......... 12 9. absolute maximum ratings ................................ ................................ ................................ ..................... 19 9.1. absolute maximum ratings ................................ ................................ ................................ ........................ 19 9.2. operating conditions ................................ ................................ ................................ ................................ .. 19 10. electrical chara cteristics ................................ ................................ ................................ ................ 20 10.1. general parameters ................................ ................................ ................................ ................................ . 20 10.2. analog signal level and gain parameters ................................ ................................ ............................... 21 10.3. analog distortion and noise parameters ................................ ................................ ................................ .. 22 10.4. analog input and output amplifier para meters ................................ ................................ ........................ 23 10.5. digital i/o ................................ ................................ ................................ ................................ .................. 25 10.5.1. ? - law encode decode chatacteristics ................................ ................................ ............................. 25 10.5.2. a - law encode decode characteristics ................................ ................................ ............................ 26 10.5.3. pcm codes for zero and full scale ................................ ................................ ................................ . 27 10.5.4. pcm codes for 0dbm0 output ................................ ................................ ................................ ......... 27 11. typical applicat ion circuit ................................ ................................ ................................ .................. 28 12. package specificatio n ................................ ................................ ................................ ........................... 30 12.1. 24l sop - 300mil ................................ ................................ ................................ ................................ ....... 30 12.2. 24l ssop - 209 mil ................................ ................................ ................................ ................................ .... 31 13. ordering information ................................ ................................ ................................ ................................ .... 32 14. version history ................................ ................................ ................................ ................................ ........ 33 www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 4 - january 201 1 5. pin configuration w 6 8 1 1 s i n g l e c h a n n e l v o i c e c o d e c v d d a a o a i - a i + v a g v r e f r o - p a i p a o - p a o + v s s a p c m r u / a l a w f s r f s t v d d d p c m t n c n c 2 3 4 5 6 7 8 1 1 0 1 5 1 7 1 6 1 8 9 2 3 2 2 2 1 2 0 1 9 2 4 v s s d b c l k r p u i m c l k 1 2 1 3 1 4 1 1 b c l k t www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 5 - january 201 1 6. pin description pin name pin no. ssop sop v dd * functionality v ref 1 a this pin is used to bypass the on - chip 2.5v v oltage reference. it needs to be decoupled to v ssa through a 0.1 ? f ceramic decoupling capacitor. no external loads should be tied to this pin. ro - 2 a inverting output of the receive smoothing filter. this pin can typically drive a 2 k ? load to 1.575 vol t peak referenced to the analog ground level. pai 3 a this pin is the inverting input to the power amplifier. its dc level is at the v ag voltage. pao - 4 a inverting power amplifier output. this pin can drive a 300 ? load to 1.575 volt peak referenced to the v ag voltage level. pao+ 5 a non - inverting power amplifier output. this pin can drive a 300 ? load to 1.575 volt peak referenced to the v ag voltage level. v dda 6 a analog power supply. this pin should be decoupled to v ssa with a 0.1 ? f ceramic capacito r. nc 7 not connected v ddd 8 d digital power supply. this pin should be decoupled to v ssd with a 0.1 ? f ceramic capacitor. for correct operation, v ddd value should always be lower than v dda . fsr 9 d 8 khz frame sync input for the pcm receive section. th is pin also selects channel 0 or channel 1 in the gci and idl modes. it can also be connected to the fst pin when transmit and receive are synchronous operations. pcmr 10 d pcm input data receive pin. the data needs to be synchronous with the fsr and bclk r pins. bclkr 11 d pcm receive bit clock input pin. this pin also selects the interface mode. the gci mode is selected when this pin is tied to v ssd . the idl mode is selected when this pin is tied to v ddd . this pin can also be tied to the bclkt when trans mit and receive are synchronous operations. pui 12 d power up input signal. when this pin is tied to v ddd , the part is powered up. when tied to v ssd , the part is powered down. mclk 13 d system master clock input. possible input frequencies are 256 khz, 5 12 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz & 4096 khz. for a better performance, it is recommended to have the mclk signal synchronous and aligned to the fst signal. this is a requirement in the case of 256 and 512 khz frequencies. bclkt 14 d pcm tra nsmit bit clock input pin. pcmt 15 d pcm output data transmit pin. the output data is synchronous with the fst and bclkt pins. fst 16 d 8 khz transmit frame sync input. this pin synchronizes the transmit data bytes. www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 6 - january 201 1 pin name pin no. ssop sop v dd * functionality v ssd 17 d this is the digital supply ground. this pin should be connected to 0v. nc 18 not connected v ssa 19 a this is the analog supply ground. this pin should be connected to 0v. ? /a - law 20 d compander mode select pin. ? - law companding is selected when this pin is tied to v ddd . a - law co mpanding is selected when this pin is tied to v ssd . ao 21 a analog output of the first gain stage in the transmit path. ai - 22 a inverting input of the first gain stage in the transmit path. ai+ 23 a non - inverting input of the first gain stage in the tr ansmit path. v ag 24 a mid - supply analog ground pin, which supplies a 2.5 volt reference voltage for all - analog signal processing. this pin should be decoupled to v ssa with a 0.01 ? f capacitor. this pin becomes high impedance when the chip is powered down. * these columns represent whether the pin is driven by analog (a) or digital (d) power supply. www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 7 - january 201 1 7. functional descri ption W6811 is a single - rail, single channel pcm codec for voiceband applications. the codec complies with the specifications of the itu - t g.712 recommendation. the codec also includes a complete ? - law and a - law compander. the ? - law and a - law companders are designed to comply with the specifications of the itu - t g.711 recommendation. the block diagram in section 3 shows the main compon ents of the W6811. the chip consists of a pcm interface, which can process long and short frame sync formats, as well as gci and idl formats. the pre - scaler of the chip provides the internal clock signals and synchronizes the codec sample rate with the ext ernal frame sync frequency. the power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. the main code c block diagram is shown in section 3. figure 7.1 the W6811 signal path 7.1. t ransmit p ath the a - to - d path of the codec contains an analog input amplifier with externally configurable gain setting (see application examples in section 11) . the device has an input operational amplifier whose output is the input to the encoder section. if the input amplifier is not required for operation it can be powered down and bypassed. in that case a single ended input signal can be applied to the ao pi n or the ai - pin. the ao pin becomes high input impedance when the input amplifier is powered down. the input amplifier can be powered down by connecting pao+ pao 8 ? /a - cont r ai+ ai - w ? /a - cont r o l ao + ro - - va g ant - aliasi filter = 3400 hz ant i - aliasi ng filter f c = 200 hz high pas s filt e sm ooth i ng filter 2 hz smooth i ng filter 1 8 ? /a control 8 ? /a - control pai v ag ant - aliasing filter - aliasing filter ant - filt er high pass filter smoothing filter filter smoothing filter filter receive path transmit path + - - + + - + - - a/d converter d/a converter f c = 3400hz f c = 3400hz c = 200hz f www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 8 - january 201 1 the ai+ pin to v dda or v ssa . the ao pin is selected as an input when ai+ is tied to v dda and the ai - p in is selected as an input when ai+ is tied to v ssa (see table 7.1). ai+ input amplifier input vdda powered down ao 1.2 to vdda - 1.2 powered up ai+, ai - vssa powered down ai - table 7.1 input amplifier modes of operation when the input amplifier is pow ered down, the input signal at ao or ai - needs to be referenced to the analog ground voltage v ag . the output of the input amplifier is fed through a 3.4 khz switched capacitor low pass filter to prevent aliasing of input signals above 4 khz, due to the sa mpling at 8 khz. the output of the 3.4 khz low pass filter is filtered by a high pass filter with a 200 hz cut - off frequency. the filters are designed according to the recommendations in the g.712 itu - t specification. from the output of the high pass filte r the signal is digitized. the signal is converted into a compressed 8 - bit digital representation with either ? - law or a - law format. the ? - law or a - law format is pin - selectable through the ? /a - law pin. the compression format can be selected according to ta ble 7.2. ? ? ? - law or a - law samples are fed to the pcm interface for serial transmission at the data rate supplied by the external bit clock bclkt. 7 .2. r eceive p ath the 8 - bit digital input samples for the d - to - a path are serially shifted in by the pcm interface and converted to parallel data bits. during every cycle of the frame sync fsr, the parallel data bits are fed through the pin - selectable ? - law or a - law expander and converted to analog samples. the mode of expansion is selected by the ? /a - law pin as shown in table 7.2. the analog samples are filtered by a low - pass smoothing filter with a 3.4 khz cut - off frequency, according to the itu - t g.712 sp ecification. a sin(x)/x compensation is integrated with the low pass smoothing filter. the output of this filter is buffered to provide the receive output signal ro - . the ro - output can be externally connected to the pai pin to provide a differential outpu t with high driving capability at the pao+ and pao - pins. by using external resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. if the transmit power amplifier is not in use, it can be powered down by co nnecting pai to v dda . www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 9 - january 201 1 7.3. p ower m anagement 7.3.1. analog supply the power supply for the analog part of the W6811 needs to be 5v +/ - 10%. this supply voltage is connected to the v dda pin. the v dda pin needs to be decoupled to ground through a 0.1 ? f cera mic capacitor. 7.3.2. digital supply the power supply for the digital part of the W6811 needs to be 3v +/ - 10%. this supply voltage is connected to the v ddd pin. the v ddd pin needs to be decoupled to ground through a 0.1 ? f ceramic capacitor. 7.3.3. anal og ground reference bypass the system has an internal precision voltage reference which generates the 2.5v mid - supply analog ground voltage. this voltage needs to be decoupled to v ssa at the v ref pin through a 0.1 ? f ceramic capacitor. 7.3.4. analog groun d reference voltage output the analog ground reference voltage is available for external reference at the v ag pin. this voltage needs to be decoupled to v ssa through a 0.01 ? f ceramic capacitor. the analog ground reference voltage is generated from the vol tage on the v ref pin and is also used for the internal signal processing. 7.4. pcm i nterface the pcm interface is controlled by pins bclkr, fsr, bclkt & fst. the input data is received through the pcmr pin and the output data is transmitted through the pc mt pin. the modes of operation of the interface are shown in table 7.3. bclkr fsr interface mode 64 khz to 4.096 mhz 8 khz long or short frame sync vssd vssd isdn gci with active channel b1 vssd vddd isdn gci with active channel b2 vddd vssd isdn idl with active channel b1 vddd vddd isdn idl with active channel b2 table 7.3 pcm interface mode selections www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 10 - january 201 1 7.4.1. long frame sync the long frame sync or short frame sync interface mode can be selected by connecting the bclkr or bclkt pin to a 64 khz to 4 .096 mhz clock and connecting the fsr or fst pin to the 8 khz frame sync. the device synchronizes the data word for the pcm interface and the codec sample rate on the positive edge of the frame sync signal. it recognizes a long frame sync when the fst pin is held high for two consecutive falling edges of the bit - clock at the bclkt pin. the length of the frame sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 ? sec. during data transmission in the long frame syn c mode, the transmit data pin pcmt will become low impedance when the frame sync signal fst is high or when the 8 bit data word is being transmitted. the transmit data pin pcmt will become high impedance when the frame sync signal fst becomes low while the data is transmitted or when half of the lsb is transmitted. the internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. to avoid bus collisions, the pcmt pin will be high impedance for two frame sync cycles after every power down state. more detailed timing information can be found in the interface timing section. 7.4.2. short frame sync the W6811 operates in the short frame sync mode when the frame sync signal at pin fst is high for one and only one falling edge of the bit - clock at the bclkt pin. on the following rising edge of the bit - clock, the W6811 starts clocking out the data on the pcmt pin, which will also change from high to low impedance state. the data transmit p in pcmt will go back to the high impedance state halfway through the lsb. the short frame sync operation of the W6811 is based on an 8 - bit data word. when receiving data on the pcmr pin, the data is clocked in on the first falling edge after the falling ed ge that coincides with the frame sync signal. the internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. to avoid bus collisions, the pcmt pin will be high impedance for t wo frame sync cycles after every power down state. more detailed timing information can be found in the interface timing section. 7.4.3. general circuit interface (gci) the gci interface mode is selected when the bclkr pin is connected to v ssd for two or more frame sync cycles. it can be used as a 2b+d timing interface in an isdn application. the gci interface consists of 4 pins : fsc (fst), dcl (bclkt), dout (pcmt) & din (pcmr). the fsr pin selects channel b1 or b2 for transmit and receive. data transitio ns occur on the positive edges of the data clock dcl. the frame sync positive edge is aligned with the positive edge of the data clock dclk. the data rate is running half the speed of the bit - clock. the channels b1 and b2 are transmitted consecutively. the refore, channel b1 is transmitted on the first 16 clock cycles of dcl and b2 is transmitted on the second 16 clock cycles of dcl. for more timing information, see the timing section. www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 11 - january 201 1 7.4.4. interchip digital link (idl) the idl interface mode is selected w hen the bclkr pin is connected to v ddd for two or more frame sync cycles. it can be used as a 2b+d timing interface in an isdn application. the idl interface consists of 4 pins : idl sync (fst), idl clk (bclkt), idl tx (pcmt) & idl rx (pcmr). the fsr pin s elects channel b1 or b2 for transmit and receive. the data for channel b1 is transmitted on the first positive edge of the idl clk after the idl sync pulse. the idl sync pulse is one idl clk cycle long. the data for channel b2 is transmitted on the elevent h positive edge of the idl clk after the idl sync pulse. the data for channel b1 is received on the first negative edge of the idl clk after the idl sync pulse. the data for channel b2 is received on the eleventh negative edge of the idl clk after the idl sync pulse. the transmit signal pin idl tx becomes high impedance when not used for data transmission and also in the time slot of the unused channels. for more timing information, see the timing section. 7.4.5. system timing the system can work at 256 kh z, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz & 4096 khz master clock rates. the system clock is supplied through the master clock input mclk and can be derived from the bit - clock if desired. an internal pre - scaler is used to generate a fixed 256 khz and an 8 khz sample clock for the internal codec. the pre - scaler measures the master clock frequency versus the frame sync frequency and sets the division ratio accordingly. if the frame sync is low for the entire frame sync period while the mclk and bclk pin clock signals are still present, the W6811 will enter the low power standby mode. another way to power down is to set the pui pin to low. when the system needs to be powered up again, the pui pin needs to be set to high and the frame sync pulse needs t o be present. it will take two frame sync cycles before the pin pcmt will become low impedance. www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 12 - january 201 1 8. timing diagrams figure 8.1 long frame sync pcm timing f st b c l k t d7 d6 d5 d4 d3 d2 d1 pc m t m sb l sb t h id t b c k d0 t b c k h t b c k l t fs t f t f h t f t r s t f t r h t h id t b d t d t f d t d 0 1 2 3 4 5 7 8 0 1 m sb l sb f sr b c l k r t b c k d6 d5 d4 d3 d2 d1 d0 pc m r d7 t d r h t d r s t b c k h t b c k l t fs t f r f h t f r r s t f r r h 0 1 2 3 4 5 6 7 8 0 1 6 m c l k t f t r h m t f t r sm t m c k h t m c k l t m c k t r ise t f a l l t f sl t f sl www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 13 - january 201 1 symbol description min typ max unit 1/t fs fst, fsr frequency --- 8 --- khz t fsl fst / fsr mi nimum low width 1 t bck sec 1/t bck bclkt, bclkr frequency 64 --- 4096 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 50 --- --- ns t ftrh bclkt 0 falling edge to fst rising edge hold time 20 --- --- ns t ftrs f st rising edge to bclkt 1 falling edge setup time 80 --- --- ns t ftfh bclkt 2 falling edge to fst falling edge hold time 50 --- --- ns t fdtd fst rising edge to valid pcmt delay time --- --- 60 ns t bdtd bclkt rising edge to valid pcmt delay time --- --- 60 ns t hid delay time from the later of fst falling edge, or bclkt 8 falling edge to pcmt output high impedance 10 --- 60 ns t frrh bclkr 0 falling edge to fsr rising edge hold time 20 --- --- ns t frrs fsr rising edge to bclkr 1 falling edge setup time 8 0 --- --- ns t frfh bclkr 2 falling edge to fsr falling edge hold time 50 --- --- ns t drs valid pcmr to bclkr falling edge setup time 0 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns table 8.1 long frame sync pcm timing parameters 1 t fsl must be at least ? t b ck www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 14 - january 201 1 figure 8.2 short frame sync pcm timing d7 d6 d5 d4 d3 d2 d1 m sb l sb t b c k d0 t b c k h t b c k l t fs t f t r s t f t r h t h id t b d t d 0 1 2 3 4 5 6 7 8 0 1 f st b c l k t pc m t t b d t d t f t f h -1 t f t f s m sb l sb t b c k d6 d5 d4 d3 d2 d1 d0 d7 t d r h t d r s t b c k h t b c k l t fs t f r r s t f r r h 0 1 2 3 4 5 6 7 8 0 1 f sr b c l k r pc m r t f r f h -1 t f r f s m c l k t f t r h m t f t r sm t m c k h t m c k l t m c k t r ise t f a l l www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 15 - january 201 1 symbol description min typ max unit 1/t fs fst, fsr frequency --- 8 --- khz 1/t bck bclkt, bclkr frequency 64 --- 4096 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 5 0 --- --- ns t ftrh bclkt C ftrs fst rising edge to bclkt 0 falling edge setup time 80 --- --- ns t ftfh bclkt 0 falling edge to fst falling edge hold time 50 --- --- ns t ftfs fst falling edge to bclkt 1 falling edge setup time 50 --- --- ns t bdtd bclkt rising edge to valid pcmt delay time 10 --- 60 ns t hid delay time from bclkt 8 falling edge to pcmt output high impedance 10 --- 60 ns t frrh bclkr C frrs fsr rising edge to bclkr 0 falling edge setup time 80 --- --- ns t frfh bclkr 0 falling edge to fsr falling edge hold time 50 --- --- ns t frfs fsr falling edge to bclkr 1 falling edge setup time 50 --- --- ns t drs valid pcmr to bclkr fa lling edge setup time 0 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns table 8.2 short frame sync pcm timing parameters www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 16 - january 201 1 figure 8.3 idl pcm timing symbol description min typ max unit 1/t fs fst frequency --- 8 --- khz 1/t bck b clkt frequency 256 --- 4096 khz t bckh bclkt high pulse width 50 --- --- ns t bckl bclkt low pulse width 50 --- --- ns t fsrh bclkt C fsrs fst rising edge to bclkt 0 falling edge setup time 60 --- --- ns t fsfh bclkt 0 falling edge to fst falling edge hold time 20 --- --- ns t bdtd bclkt rising edge to valid pcmt delay time 10 --- 60 ns t hid delay time from the bclkt 8 falling edge (b1 channel) or bclkt 18 falling edge (b2 channel) to pcmt output h igh impedance 10 --- 50 ns t drs valid pcmr to bclkt falling edge setup time 20 --- --- ns t drh pcmr hold time from bclkt falling edge 75 --- --- ns table 8.3 idl pcm timing parameters f st b c l k t pc m t pc m r d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t fs t f sr h t f sf h t f sr s t b d t d t b d t d t b d t d t b d t d t h id t h id t d r s t d r s t d r h t d r h b c h = 0 b 1 c hannel b c h = 1 b 2 c hannel m sb m sb m sb m sb l sb l sb l sb l sb t b c k t b c k h t b c k l -1 www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 17 - january 201 1 figure 8.4 gci pcm timing symbol description min typ max unit 1/ t fst fst frequency --- 8 --- khz 1/t bck bclkt frequency 512 --- 6176 khz t bckh bclkt high pulse width 50 --- --- ns t bckl bclkt low pulse width 50 --- --- ns t fsrh bclkt 0 falling edge to fst rising edge hold time 20 --- --- ns t fsrs fst rising edge t o bclkt 1 falling edge setup time 60 --- --- ns t fsfh bclkt 1 falling edge to fst falling edge hold time 20 --- --- ns t fdtd fst rising edge to valid pcmt delay time --- --- 60 ns t bdtd bclkt rising edge to valid pcmt delay time --- --- 60 ns t hid dela y time from the bclkt 16 falling edge (b1 channel) or bclkt 32 falling edge (b2 channel) to pcmt output high impedance 10 --- 50 ns t drs valid pcmr to bclkt rising edge setup time 20 --- --- ns t drh pcmr hold time from bclkt rising edge --- --- 60 ns ta ble 8.4 gci pcm timing parameters f st b c l k t pc m t pc m r d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 t fs t f d t d t b d t d t b d t d t b d t d t h id t h id t d r s t d r s t d r h t d r h b c h = 0 b 1 c hannel b c h = 1 b 2 c hannel m sb m sb m sb m sb l sb l sb l sb l sb t f sr h t f sf h t f sr s t b c k t b c k h t b c k l 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 18 - january 201 1 symbol description min typ max unit 1/t mck master clock frequency --- 256 512 1536 1544 2048 2560 4096 --- khz t mckh / t mck mclk duty cycle for 256 khz operation 45% 55% t mckh minimum pulse width high for mclk(512 khz or higher) 50 --- --- ns t mckl minimum pulse width low for mclk (512 khz or higher) 50 --- --- ns t ftrhm mclk falling edge to fst rising edge hold time 50 --- --- ns t ftrsm fst rising edge to mclk falling edge setup time 50 --- --- ns t rise rise ti me for all digital signals --- --- 50 ns t fall fall time for all digital signals --- --- 50 ns table 8.5 general pcm timing parameters www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 19 - january 201 1 9. absolute maximum ratings 9.1. a bsolute m aximum r atings condition value junction temperature 150 0 c storage tempera ture range - 65 0 c to +150 0 c voltage applied to any pin analog digital (v ssa - 0.3v) to (v dda + 0.3v) (v ssd - 0.3v) to (v ddd + 0.3v) voltage applied to any pin analog (input current limited to +/ - 20 ma) digital (v ssa C 1.0v) to (v dda + 1.0v) (v ssd C 1.0v) to (v ddd + 1.0v) v dda - v ssa ; v ddd - v ssd - 0.5v to +6v v ddd C v dda 2 < 0.3v 1. stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functiona l operation is not implied at these conditions. 2. at any time, the digital power supply should not be higher the 0.3v from the analog power supply. 9.2. o perating c onditions condition value industrial operating temperature - 40 0 c to +85 0 c analog supply voltage (v dda ) +4.5v to +5.5v digital supply voltage (v ddd ) +2.7v to +3.3v ground voltage (v ssa, v ssd ) 0v note : exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 20 - january 201 1 10 . electrical charact eristics 10.1. g eneral p arameters symbol parameters conditions min (2) typ (1) max (2) units v il input low voltage 0.5 v v ih input high voltage 2.2 v v ol pcmt output low voltage i ol = 1.6 ma 0.4 v v oh pcmt output high voltag e i ol = - 1.6 m a v ddd C 0.5 v i dda i ddd v dda current (operating) - adc+dac pui = 1 fsx running mclk running 5.5 25 8 1000 ma ? a i sba i sbd v cca current (standby) pui = 1 fsx = 0 mclk running 200 0.2 500 100 na ? a i pda i pdd v cca current (power down) v c cd current (power down) pui = 0 pui = 0 200 200 500 500 na n a i il input leakage current v ssd W6811 single channel voicecodec revision a1 5 - 21 - january 201 1 10.2. a nalog s ignal l evel and g ain p arame ters v dda =5v ? 10%; v ssa =0v; t a = - 40 ? c to +85 ? c; all analog signals referred to v ag ; mclk=bclk= 2.048 mhz; fst=fsr=8khz synchronous operation. parameter sym. condition typ. transmit (a/d) receive (d/a) unit min. max. min. max. absolute level l abs 0 dbm0 = 0dbm @ 600 ? 1.096 --- --- --- --- v pk max. transmit level t xmax 3.17 dbm0 for ? - law 3.14 dbm0 for a - law 1.579 1.573 --- --- --- --- --- --- --- --- v pk v pk absolute gain (0 dbm0 @ 1020 hz; t a =+25 ? c) g abs 0 dbm0 @ 1020 hz; t a =+25 ? c 0 - 0.25 +0.25 - 0.25 +0.25 db absolute gain variation with temperature g abst t a =0 ? c to t a =+70 ? c t a = - 40 ? c to t a =+85 ? c 0 - 0.03 - 0.05 +0.03 +0.05 - 0.03 - 0.05 +0.03 +0.05 db frequency response, relative to 0dbm0 @ 1020 hz g rtv 15 hz 50 hz 60 hz 200 hz 300 to 3000 hz 3300 hz 3400 hz 3600 hz 4000 hz 4600 hz to 100 khz --- --- --- --- --- --- --- --- --- --- --- --- --- - 1.0 - 0.20 - 0.35 - 0.8 --- --- --- - 40 - 30 - 26 - 0.4 +0.15 +0.15 0 0 - 14 - 32 - 0.5 - 0.5 - 0.5 - 0.5 - 0.20 - 0.35 - 0.8 --- --- --- 0 0 0 0 +0.15 +0.15 0 0 - 14 - 30 db gain variation vs. level tone (1020 hz relative to C 10 dbm0) g lt +3 to C 40 dbm0 - 40 to C 50 dbm0 - 50 to C 55 dbm0 --- --- --- - 0.3 - 0.6 - 1.6 +0.3 +0.6 +1.6 - 0.2 - 0.4 - 1.6 +0.2 +0.4 +1.6 db www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 22 - january 201 1 10.3. a nalog d istortion and n oise p arameters v dda =5v ? 10%; v ssa =0v ; t a = - 40 ? c to +85 ? c; all analog signals referred to v ag ; mclk=bclk= 2.048 mhz; fst=fsr=8khz synchronous operation. parameter sym. condition transmit (a/d) receive (d/a) unit min. typ. max . min. typ. max. total distortion vs. level tone (1020 hz, ? - law, c - message weighted) d lt ? +3 dbm0 0 dbm0 to - 30 dbm0 - 40 dbm0 - 45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbc total distortion vs. level tone (1020 hz, a - law, psophometric weighted) d lta +3 dbm0 0 d bm0 to - 30 dbm0 - 40 dbm0 - 45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbp spurious out - of - band at ro - (300 hz to 3400 hz @ 0dbm0) d spo 4600 hz to 7600 hz 7600 hz to 8400 hz 8400 hz to 100000 hz --- --- - -- --- --- --- --- --- --- --- --- --- --- --- --- - 30 - 40 - 30 db spurious in - band (700 hz to 1100 hz @ 0dbm0) d spi 300 to 3000 hz --- --- - 47 --- --- - 47 db intermodulation distortion (300 hz to 3400 hz C 4 to C 21 dbm0 d im two tones --- --- - 41 --- - -- - 41 db crosstalk (1020 hz @ 0dbm0) d xt --- --- - 75 --- --- - 75 dbm0 absolute group delay ? abs 1200 hz --- --- 360 --- --- 240 ? sec group delay distortion (relative to group delay @ 1200 hz) ? d 500 hz 600 hz 1000 hz 2600 hz 2800 hz --- --- --- --- -- - --- --- --- --- --- 750 380 130 130 750 --- --- --- --- --- --- --- --- --- --- 750 370 120 120 750 ? sec idle channel noise n idl ? - law; c - message a - law; psophometric --- --- --- --- 22 - 68 --- --- --- --- 13 - 78 dbrnc0 dbm0p www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 23 - january 201 1 10.4. a nalog i nput and o u tput a mplifier p arameters v dda =5v ? 10%; v ssa =0v; t a = - 40 ? c to +85 ? c; all analog signals referred to v ag ; parameter sym. condition min. typ. max. unit. ai input offset voltage v off,ai ai+, ai - --- --- ? 25 mv ai input current i in,ai ai+, ai - --- ? 0.1 ? 1.0 ? a ai input resistance r in,ai ai+, ai - to v ag 10 --- --- m ? ai input capacitance c in,ai ai+, ai - --- --- 10 pf ai common mode input voltage range v cm,ai ai+, ai - 1.2 --- v dda - 1.2 v ai common mode rejection ratio cmrr ti ai+, ai - --- 60 --- db ai amp gai n bandwidth product gbw ti ao, r ld ? 10k ? --- 2150 --- khz ai amp dc open loop gain g ti ao, r ld ? 10k ? --- 95 --- db ai amp equivalent input noise n ti c - message weighted --- - 24 --- dbrnc ao output voltage range v tg r ld =10k ? to v ag r ld =2k ? to v ag 0.5 1.0 --- --- v dda - 0.5 v dda - 1.0 v load resistance r ldtgro ao, ro to v ag 2 --- --- k ? load capacitance c ldtgro ao, ro --- --- 100 pf ao & ro output current i out1 0.5 ? ao,ro - ? v dda - 0.5 ? 1.0 --- --- ma ro - output resistance r ro - ro - , 0 to 3400 hz --- 1 --- ? ro - output offset voltage v off,ro - ro - to v ag --- --- ? 25 mv analog ground voltage v ag relative to v ssa 2.429 2.5 2.573 v v ag output resistance r vag within ? 25mv change --- 2.5 12.5 ? www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 24 - january 201 1 parameter sym. condition min. typ. max. unit. power supply rejection ratio (0 to 100 khz to v dda , c - message) psrr trans mit receive 30 30 80 75 --- --- dbc pai input offset voltage v off,pai pai --- --- ? 20 mv pai input current i in,pai pai --- ? 0.05 ? 1.0 ? a pai input resistance r in,pai pai to v ag 10 --- --- m ? pai amp gain bandwidth product gbw pi pao - no load --- 1000 -- - khz output offset voltage v off,po pao+ to pao - --- --- ? 50 mv load resistance r ldpo pao+, pao - differentially 300 --- --- ? load capacitance c ldpo pao+, pao - differentially --- --- 1000 pf po output current i outpo 0.5 ? ao,ro - ? v dda - 0.5 ? 10.0 --- --- ma po output resistance r po pao+ to pao - --- 1 --- ? po differential gain g po r ld =300 ? , +3dbm0, 1 khz, pao+ to pao - - 0.2 0 +0.2 db po differential signal to distortion c - message weighted d po z ld =300 ? z ld =100nf + 100 ? z ld =100nf + 20 ? 45 --- --- 60 40 4 0 --- --- --- dbc po power supply rejection ratio (0 to 25 khz to v dda , differential out) psrr po 0 to 4 khz 4 to 25 khz 40 --- 55 40 --- --- db www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 25 - january 201 1 10.5. d igital i/o 10.5.1. ? normalized encode decision levels digital co de normalized decode levels d7 d6 d5 d4 d3 d2 d1 d0 sign chord chord chord step step step step 8159 7903 : 4319 4063 : 2143 2015 : 1055 991 : 511 479 : 239 223 : 103 95 : 35 31 : 3 1 0 1 0 0 0 0 0 0 0 8031 : 1 0 0 0 1 1 1 1 4191 : 1 0 0 1 1 1 1 1 2079 : 1 0 1 0 1 1 1 1 1023 : 1 0 1 1 1 1 1 1 495 : 1 1 0 0 1 1 1 1 231 : 1 1 0 1 1 1 1 1 99 : 1 1 1 0 1 1 1 1 33 : 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 0 notes: sign bit = 0 for negative values, sign bit = 1 for positive values www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 26 - january 201 1 10.5.2. a - law encode decode characteristics normalized encode decision levels digital code normalized decode levels d7 d6 d5 d4 d3 d2 d1 d0 sign cho rd chord chord step step step step 4096 3968 : 2048 2048 : 1088 1024 : 544 512 : 272 256 : 136 128 : 68 64 : 2 0 1 0 1 0 1 0 1 0 4032 : 1 0 1 0 0 1 0 1 2112 : 1 0 1 1 0 1 0 1 1056 : 1 0 0 0 0 1 0 1 528 : 1 0 0 1 0 1 0 1 264 : 1 1 1 0 0 1 0 1 132 : 1 1 1 0 0 1 0 1 66 : 1 1 0 1 0 1 0 1 1 notes: 1. sign bit = 0 for negative values, sign bit = 1 for positive values 2. digital code includes inversion o f all even number bits www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 27 - january 201 1 10.5.3. pcm codes for zero and full scale level ? + full scale 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - full scale 0 000 0000 0 010 1010 10.5.4. pcm codes for 0dbm0 output sample ? 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100 www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 28 - january 201 1 11. typical applicat ion circuit figure 11.1 typical circuit for differential analog i/os figure 11.2 typical circuit for single ended analog i/os power control 1.0 uf - W6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mclk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa 1.0 uf pcm in 27k differential audio in 2.048 mhz bit clock 27k 27k 0.1 uf - 27k 0.1 uf 27k pcm out 27k +5vdc +3vdc + 0.01 uf 0.1 uf 8 khz frame sy nc + differential audio out rl > 150 ohms mode select pcm out 1.0 uf 8 khz frame sy nc W6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mclk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa 27k 0.1 uf +3vdc pcm in 1.0 uf 0.1 uf 0.01 uf audio in 27k audio out rl > 150 ohms 27k 27k 27k 2.048 mhz bit clock 100 uf +5vdc 27k 0.1 uf audio out rl > 2k ohms power control mode select www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 29 - january 201 1 figure 11.3 handset interface figure 11.4 transformer interface circuit in gci mod e 100pf 3.9k microphone 0.1 uf 1.0 uf + 62k 1.5k 1k 1.0 uf 0.1 uf 1.5k 2.048 mhz bit clock W6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mclk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa power control +5vdc 0.01 uf 27k 100pf speaker 8 khz frame sy nc 0.1 uf pcm out 3.9k electret pcm in 62k mode select 22 uf +3vdc 27k 27k 0.1 uf pcm in W6811 6 17 12 20 16 14 15 13 10 11 9 21 22 23 24 1 2 5 3 4 8 19 vdda vssd pui u/a fst bclkt pcmt mclk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- vddd vssa pcm out 600 ohm 1:1 27k 0.01 uf 2.048 mhz bit clock transformer 0.1 uf 27k 0.1 uf 8 khz frame sy nc 1.0 uf 27k +5vdc power control 27k 600 +3vdc mode select b1/b2 select www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 30 - january 201 1 12. package specificatio n 12. 1 . 24l sop - 300 mil small outline package (same as sog & soic) dimensions symbol dimension (mm) dimension (inch) min. max. min. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0. 33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 e 7.40 7.60 0.291 0.299 d 15.20 15.60 0.598 0.614 e 1.27 bsc 0.050 bsc h e 10.00 10.65 0.394 0.419 y 0.10 0.004 l 0.10 1.27 0.016 0.050 0 0o 8o 0 8o e 1 24 13 12 www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 31 - january 201 1 12.2 . 24l ssop - 209 mil shrink small outline packag e dimensions www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 32 - january 201 1 13. o rdering i nformation nuvoton part number description when ordering W6811 series devices, please refer to the following part numbers. part number W6811isg W6811irg package type: s = 24 - lead plastic small outline package (sog/sop) r = 24 - lead plastic small outline package (ssop) product family W6811 product W6811i _ _ package material: g = pb - free (rohs) package www.datasheet.co.kr datasheet pdf - http://www..net/
W6811 single channel voicecodec revision a1 5 - 33 - january 201 1 14. vers ion history version date page description a10 october 2003 34 changed the package dimension of the ssop24 package a11 april 2005 41 add important notice a12 september, 2005 2 11, 12 22 23 23 29, 30 35 added reference to pb - free rohs packaging capitaliz ed logic high/low extended conditions on table 10.2. extended conditions on table 10.3. corrected idle channel noise min/max and units. improved application diagrams added g package ordering code a13 january 2009 24 35 35 idle channel noise value updated pdip package no long supported leaded packages no longer supported a14 march 2010 various tssop package no long er supported a15 january 2011 30 sop - 24 package diagram updated important notice nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, nuvoton products are not intended for applications wherein failure of nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environme ntal damage could occur. nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulting from such improper use or sales. the information contained in this datasheet may be subject to change without notice. it is the responsibility of the customer to check the nuvoton website ( www.nuvoto n .com ) periodically for the latest version of this document, and any errata sheets that may be generated between datasheet revisions. www.datasheet.co.kr datasheet pdf - http://www..net/

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